The present invention relates in general to a random access memory for use with a microprocessor having improved memory access time and more specifically to a dual-port shared memory in which memory access is obtained at a speed allowing contention between microprocessors to be resolved in a manner transparent to the dual processors.
Random access memories are available in many different configurations and with many different features for satisfying a variety of design needs. Static and dynamic memory chips are available with various memory capacities and speeds. In general, a higher speed memory results in a higher cost per bit of memory capacity due to the usual need to rely on more complex circuit design and fabrication techniques.
Dual-port memories are employed to allow sharing of a memory by a pair of separate processors. Multiple processors are frequently used in applications where the capacity or speed of a single processor is inadequate for providing the desired system operation. The use of a shared memory may be desirable where information or variables are used by both processors in performing their separate functions. For example, a first processor may control operation of a vehicle engine while a second processor may control a vehicle transmission. The separate control functions are implemented according to a plurality of sensed system parameters, some of which are used by both processors, such as engine speed, engine torque, and vehicle speed.
Various types of dual-port random access memories are known. Some memory designs allow simultaneous access from each port while other designs require that access be granted to each port separately according to an access arbitration scheme. In the case of asynchronous, arbitrated access, any delays in retrieving information requested via an access port can be handled by causing wait states in the requesting processor to allow sufficient time for retrieval of information from the memory. The addition of wait states greatly impairs the efficiency of microprocessor system operation. Alternatively, handshaking methods can be used to coordinate memory access through the dual memory ports. However, microprocessor efficiency is again reduced because of the delay from a memory access request until access is granted using the appropriate handshaking signals.